ML310e turbo bootsきると静か。
IA32_MISC_ENABLE MSR(1A0H)の 38bit目の
Shared IDA *1 Disable (R/W)を有効にするときれる
for i in 0 1 2 3 4 5 6 7 ; do rdmsr -p$i 0x1a0 ; done wrmsr -p0 0x1a0 0x4000850089
8.7.8 IA32_MISC_ENABLE MSR
https://www-ssl.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html/
The IA32_MISC_ENABLE MSR (MSR address 1A0H) is generally shared between the logical processors in a
processor core supporting Intel Hyper-Threading Technology. However, some bit fields within IA32_MISC_ENABLE
MSR may be duplicated per logical processor. The partition of shared or duplicated bit fields within
IA32_MISC_ENABLE is implementation dependent. Software should program duplicated fields carefully on all
logical processors in the system to ensure consistent behavior.
Table 35-3. MSRs in Processors Based on Intel® Core™ Microarchitecture (Contd.)
https://www-ssl.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html/
0 Fast-Strings Enable 1 Resv 2 Resv 3 Automatic Thermal Control Circuit Enable 4 Resv 5 Resv 6 Resv 7 Performance Monitoring Available (R) 8 Resv 9 Resv 10 Resv 11 Branch Trace Storage Unavailable (ro) 12 Precise Event Based Sampling (PEBS) Unavailable (ro) 13 Resv 14 Resv 15 Resv 16 SpeedStep (rw) := 1(ena) 17 Resv 18 Enable Monitor FSM (rw) 19 Resv 20 Resv 21 Resv 22 Limit CPUID (rw) 23 # xTPR Mesg (rw) := 0(ena) 33:24 Resv 34 # XD bit (rw) := 0(ena) 35 Resv 36 Resv 37 # Unique DCU Prefetcher Disable (R/W) 38 # Shared IDA Disable (R/W) 39 # Unique IP Prefetcher Disable (R/W) 63:40 Resv
周波数制限は
cpufreq-set -c 0 -g ondemand -u 2.00GHz;
こんなかんじでok
